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fn6457 rev 0.00 page 1 of 24 september 25, 2007 fn6457 rev 0.00 september 25, 2007 ISL6113, isl6114 dual slot pci-e hot plug controllers datasheet the ISL6113, isl6114 both target the pci-express add-in card hot swap application. together with a pair of n-channel and p-channel mosfets, and two sense resistors per slot, either provides compliant hot plug pow er control to any combination of two pci-express x1, x4, x8 or x16 slots. the ISL6113, isl6114 feature a programmable current regulated (cr) maximum level for a programmable period to each voltage load so that both fault isolation protection and imperviousness to electrical transients are provided. for each +12v supply, the cr le vel is set by a resistor value depending on the needs of the pci-express connector (x1, x4, x8 or x16) to be powered. this r esistor is a sub-ohm standard value current sense re sistor one for each slot and the voltage across this resistor is compared to a 50mv reference providing a nominal cr protection level adequately above the specific slot maximum limits. the 3.3v supply uses a 15m ? sense resistor compared to a 50mv re ference to provide 3.3a of maximum regulated current t o all connector sizes. the 3.3vaux is internally monitor ed and controlled to provide a nominal maximum of 1a of aux output current. the cr period for each slot is set by a separate external capacitor on the associated cfil ter pin. once the cr period has expired, the ic th en quickly turns off its associated fets thus unloading the fa ulted card from the supply voltage rails. a nominal 3.3v must always be p resent on the auxi pin for proper ic bias; this should be the 3.3vaux supply if used, if n ot the auxi pin is tied directly to the 3vmain supply. both ics employ a card presence detecti on input that disables the main and aux enabling inputs if it is not pulled low. output voltage monitoring with both pci-e re set not and power good not reporting along with oc fault r eporting are provided. whereas the ISL6113 has the same gate drive and response characteristics as the isl6112, the isl6114 has a lower turn-on gate drive current allowing for the use of smaller compensation capacitors and t hus much faster response to way overcurrent (woc) conditions. additionally, the isl6114 does not turn-on with the cr feature invok ed as do the isl6112, ISL6113 allowing for shorter cr programmed periods.the ISL6113, isl6114 are footprint compatible for all common pins, but not entirely function compatible with the isl6112s qfn package as there are i/o differences. features ? dual pci-e slot hot swap po wer control and distribution ? highest accuracy external r sense current monitoring on main supplies ? programmable current regulation protection function for x1, x4, x8, x1 6 connectors ? programmable current regulation duration ? programmable in-rush protection during turn-on ? latch-off or retry modes after failure ? pb-free (rohs compliant) applications ? pci-express servers ? power supply distribution and control ? hot swap/electronic breaker circuits ? network hubs, routers, switches ? hot swap bays, cards and modules figure 1. typical ISL6113, isl6114 block diagram application implementation 3vgatea 3vina 12vgatea 12vina ISL6113, isl6114 3vsensea vstbyb vauxa 12vsensea 3vgateb 3vinb 12vgateb 12vinb 3senseb vauxb 12vsenseb prsnta prsntb forona foronb auxenb onb ona gpi_a0 gpi_bo gpo_a0 gpo_b0 faulta faultb pwrgda pwrgdb cfiltera perstb persta gnd 12vouta 3vouta 3voutb 12voutb cfilterb vstbya if 3.3vaux not implemented auxena if 3.3vaux not implemented o b s o l e t e p r o d u c t n o r e c o m m e n d e d r e p l a c e m e n t c o n t a c t o u r t ec h n i ca l s u p p o r t c e n t er a t 1- 88 8- i n t e r s i l o r w w w . i n t e r s i l . c o m / t sc
ISL6113, isl6114 fn6457 rev 0.00 page 2 of 24 september 25, 2007 pinout ISL6113, isl6114 (48 ld qfn) top view ordering information part number part marking temp. range ( c ) package (pb-free) pkg. dwg. # ISL6113irza ISL6113 irz -40 to +85 48 ld 7x7 qfn l48.7x7 ISL6113irza-t* ISL6113 irz -40 to +85 48 ld 7x7 qfn tape and reel l48.7x7 isl6114irza isl6114 irz -40 to +85 48 ld 7x7 qfn l48.7x7 isl6114irza-t* isl6114 irz -40 to +85 48 ld 7x7 qfn tape and reel l48.7x7 ISL6113eval1z ISL6113 evaluation platform isl6114eval1z isl6114 evaluation platform *please refer to tb347 for det ails on reel specifications. note: these intersil pb-free pl astic packaged products employ sp ecial pb-free material sets; molding compounds/die attach mater ials and 100% matte tin plate plus anneal - e3 termination finish, which is r ohs compliant and compatible with both snpb and pb-free solderi ng operations. intersil pb-free products are msl classified at pb-free peak re flow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. gnd (exposed bottom pad) 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 gnd (exposed bottom pad) gnd 3vouta vauxa 3vgatea 3vsensea gpo_a0 gpo_b0 3voutb vauxb 3vgateb 3vsenseb auxena gnd ona onb auxenb perst b prsnt a prsnt b gpi_b0 fault b cfilterb 12vgateb gnd 12vinb pwrgd b 12vsenseb force_on b 12voutb vstbyb 3vinb fault a cfiltera 12vgatea gpi_a0 12vina pwrgd a nc 12vsensea force_on a 12vouta vstbya 3vina l/r perst a nc nc nc
ISL6113, isl6114 fn6457 rev 0.00 page 3 of 24 september 25, 2007 functional block diagram (1 channel) logic vaux pwrgd thermal shutdown on/off vaux charge pump and mosfet vaux overcurrent 3vin 10.5v 2.8v 12vin 12v bias power-on reset 250s 3v uvlo 12v uvlo on /off on /off on /off on / 50mv 50mv 100mv* 100mv* vstby i ref vstby 40k ? x 2 12vgate vaux 3vgate fault pwrgd 3vout 12vout 3vpwrgd 12vpwrgd int gnd prsnt l/r gpo gpi force_on cfilter 3vin 3vsense 12vin 12vsense on auxen vstby vstby uvlo off 1.25v both a and b slots share the l/r pin. perst
ISL6113, isl6114 fn6457 rev 0.00 page 4 of 24 september 25, 2007 pin descriptions pin name function 9, 28 force_on a, force_on b asserting a force_on input low will turn on the main and aux supplies to the respec tive slot in a forced mode over riding the on input and the uv, oc and short circuit prote ctions on those outputs. uvlo protection for the vstby input is not affected by the force_on pins. asserting force_on will cause the pwrgd and fault outputs to enter their open-drain state. this input is internal ly pulled high to the vaux r ail. functionality is disabled when prsnt is high. 44, 43 ona, onb enable input for main outputs use to enable or di sable main voltage supply (12v and 3.3v) outputs. taking onx low after a fault resets the respective slots main output fault latch. functionality is disabled when prsnt is high. 45, 42 auxena, auxenb 3.3vaux enable input, enables the respectiv e vaux output. pulling auxenx low after a fault resets the associated slots vaux fault lat ch. functionality is disabled w hen prsnt is high. 5, 32 12vina,12vinb connect to 12vmain supply and high side of se nse resistor. this is one of tw o pins for kelvin connection to measure the 50mv cr vth. an undervoltage lockout prevents the i c main supply function until 12vin >10v. the current regulation threshold is set by connecting a sense resis tor between this pin and 12vsense. when the current-limit threshold of ir = 50mv is reached, the 12vgate pi n is modulated to maintain a constant 50mv voltage across the sense resistor and thereby a constant curren t is passed into the load. if the 50mv threshold is maintained for cr duration, the circuit breaker is tripped and both gate pins for the affected slot turn off the switch fets and thus turn off the supplies to the slot. 8, 29 12vsensea, 12vsenseb 12v current sense low side input. this is the second of two pin s for kelvin connection to the r sense to measure the 50mv cr vth. the cr limits are set by connecting a sense re sistor between each of these pins and associated 12vin pin. 10, 27 12vouta, 12voutb 12v output voltage monitor for uv condition. this is the voltag e input downstream of the mosfet that is delivered to the add-in card load. 12, 25 3vina, 3vinb connect to 3vmain supply and high side of sen se resistor. this provides one of two pins for kelvin connectio n to measure the 50mv cr vth. undervoltage lockout (uvlo) prevents t urn-on until 3vin >2.75v. the current regulation threshold is set by connecting a sense resistor betw een this pin and 3vsense. when the current-limit threshold of ir = 50mv is reached, the 3vgate pin is modulated to maintain a constant 50mv voltage across the sense resistor and thereby a constant current is passed into th e load. if the 50mv threshold is maintained for the cr duration, the circuit breaker is tripped and both fets for t he affected slot are turned-off. 13, 24 3vsensea, 3vsenseb 3.3v current sense lo w side input. this provides the second of two pins for kelvin connection for measuring the 50mv cr vth. the cr limits are set by connecting a sense resist or between each of these pins and associated 3vinx pin. 16, 21 3vouta, 3voutb 3.3v output voltage monitor for uv condition. this is the volta ge downstream of the mosfet that is delivered to the add-in card load. 1, 36 fault a, fault b an open drain output which is pulled low whenever the cr dura tion has expired due to an oc fault condition on any of the main or the aux supplies or in the event of an ic ov er-temperature condition. i f fault latch is invoked by a main (+12v, +3.3v) supply fault, then it is reset by pulli ng the faulted slots on pin low. if fault was asserted because of an oc fault condition on the slots aux output then pulling the auxen input low will reset the latch. both enabling inputs must be pulled low to clear a fault condit ion on both the main and vaux outputs of the same slot. internal over-temperature limit is ~+140c with a +20c h ysteresis. 15, 22 vauxa, vauxb 3.3vaux output to the pci-e slot: this outpu t connects to the vaux pin of the pci-e connector through an in ternal 0.3 ? fet. this output is current regulated to ~1a. 11, 26 vstbya vstbyb 3.3v bias input for the ic, and internal vaux switches. v vstby must always be present for proper ic bias, either from a dedicated 3.3v or 3vma in if aux supply not implemented. 41 l/r latch-off or retry bar input. tyi ng this input low invokes a pe riodic retry to turn-on afte r current regulation timer has expired on both slots. leavi ng this pin open provides a lat ch-off operational mode after cr period has expired. in this mode turn-on is initiated by cycling the appropriate en input(s). this pin is internally pulled up to vstby. 40, 39 prsnt a, prsnt b the card presence detection inpu t disables the operation of th e force_on , on and auxen inputs if not pulled to gnd. if after turn-on, the prsnt input goes high then all associated outputs (main and aux) are turned off immediately. 6, 31 pwrgd a, pwrgd b a power good not si gnal that is asserted low while all output v oltages are compliant. 4, 38 gpi_a0, gpi_b0 ~5ms debounc ed user attention input, driven by either a mechanical switch or digital signal form higher le vel controller. 48, 47 gpo_a0, gpo_b0 user attention output, that can be used to drive leds, alarms or other att ention getting devices. open dra in with 90ma pull-down capability.
ISL6113, isl6114 fn6457 rev 0.00 page 5 of 24 september 25, 2007 3, 34 12vgatea, 12vgateb 12vmain gate drive output, connects to gate of an external p-ch annel mosfet. during power-up, this pin is pulled down with a 25a (5a for isl6114) current to control th e dv/dt ramp of the output voltage to the slot. during cr, the voltage on this pin is modulated to maintain a constant current into the load. during power-down or latch-off for an overcurrent fault, this pin is pulled high to 12vin by internal sources. 14, 23 3vgatea, 3vgateb 3vmain gate drive outputs connects to gate of an external n-cha nnel mosfet. during power-up this pin charges up with a 25a (5a for isl6114) current to control the dv/dt r amp of the output voltage to the slot load. during crtim the voltage on this pin is modulated to maintain a consta nt current into the load. during power-down or latch-off for an overcurrent faul t this pin is pulled low by in ternal sources. 37, 18 perst a, perst b 100ms delayed report of main supplies output voltage compliance . 2, 35 cfiltera, cfilterb a capacitor connected between each of these pins and ground se ts the current regulated duration (tfilter) for each slot. tfilter is the amount of time for which a slot remai ns in current limit before its circuit breaker is tripped. 17, 33, 46 gnd ic ground reference 7,19, 20, 30 nc no connect pin descriptions (continued) pin name function
ISL6113, isl6114 fn6457 rev 0.00 page 6 of 24 september 25, 2007 absolute maximum ratings (note 3) thermal information 12vin, 12vsense, 12vout . . . . . . . . . . . . . . . . . . . . . . . . +14.5v vstby, 3vin, 3vsense, 3vout . . . . . . . . . . . . . . . . . . . . . . . +7v 12vgate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 12vi 3vgate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 12vi logic i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +5.5v vaux output current . . . . . . . . . . . . . . . . . .short c ircuit protected esd rating human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kv machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200v charged device model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1kv thermal resistance (typical, notes 1, 2) ? ja (c/w) ? jc (c/w) 48 ld 7x7 qfn package . . . . . . . . . . . 27 3 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . +150c maximum storage temperature range . . . . . . . . . -65c to +15 0c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp operating conditions 12vmain supply voltage range. . . . . . . . . . . . . . . . . . +12v 10% 3vmain supply voltage range. . . . . . . . . . . . . . . . . . .+3.3v 10% auxi supply voltage range . . . . . . . . . . . . . . . . . . . . .+3.3v 10% temperature range (t a ) . . . . . . . . . . . . . . . . . . . . . .-40c to +85c caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. ? ja is measured with the component mounted on a high effective the rmal conductivity test board in free air. see tech brief tb379 for details. 2. for ? jc , the case temp location is the center of the exposed metal p ad on the package underside. 3. all voltages are relative to g nd, unless otherwise specified. electrical specifications 12vin = 12v, 3vin and vstby = +3.3v, t a = t j = -40c to +85c, unless otherwise specified. parameter symbol test conditions min typ max unit main current regulation current limit threshold voltages vthilimit v in C v sense 47.5 50 52.5 mv fast-trip threshold voltages vthfast v in C v sense (ISL6113) 85 100 115 mv v in C v sense (isl6114) 140 150 160 mv vsense input current isense 0.1 a cfilter threshold voltage vfilter 1.20 1.25 1.30 v cfilter charging current nominal current limit duration = c filter x 550k ifilter v vin C v vsense > v thilimit 2 2.5 3 a tfilter cfilter open 10 s auxiliary current regulation regulated current level ilim(aux ) from end of isc(tran) to cfilter time-out 0.8 1 1.2 a output mosfet resistance vaux mosfet r ds(aux) i ds = 375ma, t j = +125c 350 m ? off-state output offset voltage vaux voff(vaux) vaux = off, t j = +125c 40 mv bias and power good supply current icc12 enabled with no load current 0.9 1.5 ma icc3.3 enabled with no load current 0.1 0.2 ma iccstby enabled with no load current 5 6 ma 12vin, 3vin, vstby undervoltage lockout thresholds vuvlo (12v) 12vin increasing 8 9 10 v vuvlo (3v) 3vin increasing 2.1 2.5 2.75 v vuvlo(stby) vstby increasing 2.8 2.9 2.96 v undervoltage lockout hysteresis 12vin, 3vin vhysuv 180 mv
ISL6113, isl6114 fn6457 rev 0.00 page 7 of 24 september 25, 2007 undervoltage lockout hysteresis vstby vhysstby 50 mv power-good undervoltage thresholds vuvth(12v) 12v out decreasing 10.15 10.5 10.75 v vuvth(3v) 3v out decreasing 2.7 2.8 2.9 v vuvth(vaux) vaux decreasing 2.55 2.8 3.0 v power-good detect hysteresis vhyspg 30 mv gate drive 12vgate voltage vgate(12v) max gate voltage when enabled 0 0.55 v ISL6113 12vgate sink current igate (12vsink) start cycle 17 25 3 5 a isl6114 12vgate sink current start cycle 3 5 7 a 12vgate source current (fault off) (absolute value) igate (12vpullup) any fault condition (vdd C vgate) = 2.5v 35 72 ma 3vgate voltage vgate(3v) min gate voltage when enabled 12v in - 0.55 12v in v ISL6113 3vgate source current igate(3vcharge) start cycle 17 25 35 a isl6114 3vgate source current start cycle 3 5 7 a 3vgate sink current (fault off) igate(3vsink) any fault conditi on vgate = 2.5v 80 105 ma analog i/o dc parameters gpo pull-down current i gpo_out 80 ma low-level input voltage on, auxen, gpi, force_on , prsnt vil 0.8 v output low voltage fault , pwrgd , gpo, perst vol iol = 3ma 0.4 v high-level input voltage on, auxen, gpi,force_on , prsnt vih 2.1 5 v internal pull-ups to vstby (note 4) rpullup 40 50 k ? 12vin, 3vin input leakage current ilkg,off xvin vstby = +3.3v, 12vin = off; 3vin = off 0.5 1 a input/output leakage current, on, auxen, gpo, force_on , perst , iil -2 2 a off-state leakage current fault , pwrgd , gpi ilkg(off) gpi i lkg for these two pins measured with vaux off -2 2 a output discharge resistance rdis (12v) 12v out = 6.0v 1400 1850 ? rdis (3v) 3v out = 1.65v 140 180 ? rdis (vaux) 3vaux = 1.65v 350 400 ? perst pull-down current when asserted. i perst onx is low 30 ma thermal protection over-temperature shutdown and reset thresholds with overcurrent on slot t over t j increasing, each slot 140 c t j decreasing, each slot 130 c over-temperature shutdown and reset thresholds, all other conditions (all outputs will latch off) t j increasing, both slots 160 c t j decreasing, both slots 150 c electrical specifications 12vin = 12v, 3vin and vstby = +3.3v, t a = t j = -40c to +85c, unless otherwise specified. (continued) parameter symbol test conditions min typ max unit
ISL6113, isl6114 fn6457 rev 0.00 page 8 of 24 september 25, 2007 i/o timing parameters 12v current limit response time t off(12v) cgate = 25pf vin C vsense = 140mv 1 2.1 s 3.3v current limit response time t off(3v) cgate = 25pf vin C vsense = 140mv 0.3 1 s vaux current limit response time t sc(tran) vaux = 0v, vstby = +3.3v 2.5 s delay from main overcurrent to fault output t prop (12v fault or 3v fault) cfilter = 0 vin C vsense = 140mv 1 s delay from vaux overcurrent to fault output t prop (vauxfault) i lim(aux) to fault output cfilter = 0 vaux output grounded 1 s on, auxen, prsnt min pulse width t min 100 ns power-on reset time after vstby becomes valid t por 250 s auto-retry period t retry r/l tied to gnd, any oc event 0.75 1.4 3 s presence detect delay to auto enable t prsnt_on prsnt = high to low 4 6.5 9 ms presence detect delay to disable t prsnt_off prsnt = low to high 2.5 s gpi to gpo propagation delay t gpi-gpo gpi high/low to gpo high/low 4 6 8 ms delay of main power good to reporting t pvperl pwrgd low to perst high . 105 145 185 ms power supply disabled to perst low t perst on low to perst low 100 ns note: 4. limits should be considered typical and are not production te sted. electrical specifications 12vin = 12v, 3vin and vstby = +3.3v, t a = t j = -40c to +85c, unless otherwise specified. (continued) parameter symbol test conditions min typ max unit
ISL6113, isl6114 fn6457 rev 0.00 page 9 of 24 september 25, 2007 typical application diagram system power supply pci-express connector +12v +3.3v vstby vstbyb vstbya vauxa 12vina 12vsensea 3vina 3vsensea 12vinb 12vsenseb 3vinb 3vsenseb 12vgatea 12vouta 3vgatea 3vouta 3vgateb 3voutb vauxb gnd gnd prsnta prsntb l/r onb ona gpi_b0 gpi_a0 force_on b force_on a auxenb auxena persta gpob gpoa 12vgateb 12voutb cfiltera cfilterb ISL6113 #c gs 22nf * r12vgatea 15 ? # c gate 22nf # c gd 6800pf 15 ? rsense^ pci express bus 3.3aux 375ma 3.3v 3.0a 12v 2.1a (x4/x8) rsense^ #c gs 22nf * r12vgateb 15 ? # c gd 6800pf rsense^ 0.015 ? #cgate 22nf *r3vgateb rsense^ 0.015 ? pci-express connector pci express data bus 3.3aux 375ma 3.3v 3.0a 12v 2.1a (x4/x8) * values for r 12vgate and r 3vgate may vary depending upon the c gs of the external mosfets. # these components are not required for ISL6113/4 operation but can be implemented for gate output slew rate control (application specific) ? bold lines indicate high current paths 4 9 2 11 26 5 8 3 10 12 13 14 16 32 29 34 27 25 24 23 21 22 17 gnd 33 46 15 15 ? *r3vgatea 0.1f 0.1f 0.1f 0.1 f 0.1f 0.1f faultb faulta pwrgdb pwrgda 1 onb ona auxenb auxena hot-plug controller 48 47 37 43 42 38 28 35 45 44 v stby c1 c2 vstby 10k x 3 10k x 4 39 40 41 gpi_b0 100k 100k 100k 100k gpi_a0 v stby force_on b force_on a faultb faulta pwrgdb pwrgda 36 31 6 v stby 10k x 4 ^ r sense value is application specific short pin gnd on connector short pin gnd on connector float for latch / gnd for retry persta 18 v stby isl6114
ISL6113, isl6114 fn6457 rev 0.00 page 10 of 24 september 25, 2007 ISL6113, isl6114 descriptions and operational explanation these two ics ta rget the dual pci-express slot application for add-in cards in s ervers. together with a pair of n and p-channel mosfets, four high precision current sense resistors and a handf ul of passive components, the ISL6113, isl6114 provide a pci-e compliant hot plug control solution. these ics use the ho t plug interface (hpi) for communicating, enabling, monitoring and reporting of uv conditions and oc and over tem perature faults. additionally they have a full complement of pci-e specific i/o. the ISL6113, isl6114 share the same footprint as their sister part, the isl6112, whi ch features both smi and hpi control and communication capabi lities, neither of these two has serial bus capabilities. w hereas the ISL6113 has the same turn-on characteristics as the isl6112, the isl6114 uses a lower level of current sourcing on the gate outputs (5a vs the ISL6113s 25a). this lower sourcing current allows the user to use less gate capacitance for in-rush current and gate ramp control than the ISL6113 to achieve similar turn-on char acteristics. this reduced capacitance in turn provides for a faster turn-off of the main supplies by the isl6114 in the event of an oc f ault than is possible with the ISL6113. bias, power-on reset and power cycling the ISL6113, isl6114 utilizes the vstby pins as the only ic bias supply source. for system s without a dedi cated 3.3v auxiliary supply, the 3vmain supp ly is to be used for the ic bias. a power-on reset (por) cycle is initiated after vstby rises above its uvlo threshol d and remains satisfied for t por , ~250s. if vstby is recycled, the ISL6113, isl6114 enters a new power-on-reset cycl e. vstby must be the first supply voltage applied followed by the main supply inputs. during t por , all outputs remain off . pci-express (pci-e) compliance requires that the connector power must be off prior to and during insertion and during removal of a pci-e board. before the add-in board is properly inserted into or removed from a connector, the fet switches are turned off via the enabling inputs (on_x and auxen_x). i n the event of an improper insertion or rem oval and to ensure that the power is off when necessary, the ISL6113, isl6114 has a present input (prsnt ) per slot that ove rrides and disables the enabling inputs if prsnt is not pulled low by having a card fully inserted into the s lot to complete the pull-down circuit. the prsnt pin must be a last to make, first to break connection to ensure compliance. enabling the vaux outputs upon asserting an auxen input, the related output turns-on the internal power switch between the vstby supply and its load. the turn-on is slew rate limited and invokes the ics current regulation feature so a s to not droop the supply due to in-rush current loading. figure 2 illustrates the ISL6113 aux turn-on performance into a 100 ? , 150f load with the in-rush load current being limited to ~1a. . standby mode standby mode is entered when one or more of the main supply inputs (12v in and/or 3v in ) is absent, below its respective uvlo threshold or off. the ISL6113, isl6114 also has 3.3v auxiliary out puts (vaux), satisfying an optional pci express requirem ent. these outputs are fed from the vstby input pins and controlled by the auxen input pins and are independent of the main outputs. should ic be in standby mode the vaux switch will function as long as v vstby is compliant. prior to standby mode, ona and onb inputs must be deassert ed or else the ISL6113, isl6114 will assert its fault outputs. enabling the main gate outputs the related auxen must be acti ve for the main supplies to be enabled otherwise they will be latched off . when a slots main supplies are off, the 12vgate pin is held high with an internal pull-up to the 12vin voltage. similarly, the 3vgate pin is internally held low to gnd. with an add-in card properly in place, when an on_x pin is signaled high, the ISL6113, isl6114 enables control of one slot turning on one pair of fets via the 3vgate and 12vgate pins. the fet gates are char ged with a + 25a (+ 5a for the isl6114) current sink/source pulling th e 12vgate pin to ground and the 3vgate pin is charged to ~12vin thereby enhancing both of the main supply fet switches. estimating in-rush current and v out slew rate at start-up the expected in-rush current c an be estimated by using equation 1: with 25a and 5a being the ga te pin charge current for figure 2. vaux turn-on r load = 10 ? , c load = 100f vaux iaux auxen ISL6113 - i inrush nominally 25 ? a c load c gate ------------------- - ?? ?? ?? = (eq. 1) isl6114 - i inrush nominally 5 ? a c load c gate ------------------- - ?? ?? ?? =
ISL6113, isl6114 fn6457 rev 0.00 page 11 of 24 september 25, 2007 the ISL6113, isl6114 respectively, c load is the load capacitance, and c gate is the total gate capacitance including c iss of the external mosfet and any external capacitance connected from the gate output pin to the gate reference, gnd or source. an estimate for the output slew rate of 3.3v outputs and 12v outputs where there is little or no external 12vgate output capacitors, can be taken from equation 2: where i lim = 50mv/r sense and c load is the load capacitance. note: as a consequence, the cr duration, t filter must be programmed to e xceed the time it takes to fully charge the output load to the input rail voltage level. main outputs (start-up delay and slew-rate control) the 3.3v outputs act as source followers. in this mode of operation, v source = [v gate C v th(on) ] until the associated output reaches 3.3 v. the voltage on the gate of the mosfet will then continue to rise until it reaches 12v, which ensures minimum r ds(on) . for the 12v outputs, when the mosfet is optionally configured as a miller integrator to adjust the v out ramp time by having a c gd , which is connected between the mosfe ts gate and drain. in this configuration, the feedback act ion from drain to gate of the mosfet causes the voltage at the drain of the mosfet to slew in a linear fashion at a rate estimat ed by equation 3: tables 1 and 2 approximate the o utput slew-rate for various values of c gate when start-up is dominated by gate capacitance (external c gate from gate pin to ground plus c gs of the external mosfet for the 3.3v rail; c gd for the 12v rail). during turn-on, the ISL6113 invokes the current regulation (cr) feature to limit inrush current whereas the isl6114 disables the cr feat ure during turn-on thus allowing a shorter programmed t filter . both ics monitor for a severe or way overcurrent (woc) condi tion such as a short at this time. note that all of these perform ance estimates and guidelines are useful only for first order time and loading expectations, as they do not look at other s ignificant loading factors. figures 3 through 11 realistica lly illustrate the discussed turn-on performance topic with the noted loading and compensation conditio ns. notice the degree of control over the in-rush current and the gate ramp rate as the c gd and c gs values are changed provid ing for highly customized turn on characteristics. in some scope shots although the c filter shows a ramping in the absence of excessive dis played loading current the c filter is responding to the other main supply current that is not displayed. all scope shots were taken from the ISL6113eval1z or isl6114eval1z platform with any component changes are noted. table 1. ISL6113 3.3v and 12v output slew-rate selection for gate capacitance dominated start-up | igate | = 25a cgate or c gd dv/dt (load) 0.01f* 2.5v/ms 0.022f* 1.136v/ms 0.047f 0.532 v/ms 0.1f 0.250v/ms * values in this range will be affected by the internal parasitic capacitances of the mosfets used and should be verified empirically. voutdv/dt i lim c load ------------------- - = (eq. 2) voutdv/dt 25 ? a c gd -------------- - = (eq. 3) ISL6113 voutdv/dt 5 ? a c gd ------------ = isl6114 table 2. isl6114 3.3v and 12v output slew-rate selection for gate capacitance dominated start-up | igate | = 5a cgate or c gd dv/dt (load) 0.01f* 0.5v/ms 0.022f* 0.23v/ms 0.047f 0.106 v/ms 0.1f 0.050v/ms * values in this range will be affected by the internal parasitic capacitances of the mosfets used and should be verified empirically. figure 3. ISL6113 12vmain start-up r load = 10 ? , c load = 470f 12 iout 12v out 12v gate c filter c gd = 6.8nf c gs = 22nf
ISL6113, isl6114 fn6457 rev 0.00 page 12 of 24 september 25, 2007 figure 4. ISL6113 3vmain start-up r load = 2 ? , c load = 470f figure 5. ISL6113 12vmain start-up r load = 10 ? , c load = 470f figure 6. ISL6113 3vmain start-up r load = 2 ? , c load = 470f 3vgate 3 v out 3 iout cfilter c gate = 22nf 12v out 12vgate c gd = 6.8nf 12iout cfilter c gs = 2.2nf 3vgate 3v out 3iout cfilter c gate = 2.2nf figure 7. ISL6113 12vmain start-up r load = 10 ? , c load = 470f figure 8. isl6114 12vmain start-up r load = 10 ? , c load = 470f figure 9. isl6114 3vmain start-up r load = 2 ? , c load = 470f 12v out 12vgate c gd = 9.8nf 12iout cfilter c gs = 2.2nf 12vout 12vgate c gd = 1.5nf 12iout cfilter c gs = 4.7nf 3 iout 3vgate 3 v out cfilter c gs = 4.7nf 3 iout
ISL6113, isl6114 fn6457 rev 0.00 page 13 of 24 september 25, 2007 current regulation (cr) function the ISL6113, isl6114 provides a current limiting function that protects the input vol tage supplies against excessive current loads, including short circuits during turn-on (main supplies shown in previous figures 3 through 11) and during static operation for both main (fig ures 12 through 15) and aux supplies (figures 16 and 17). when during static operation, any load current causes >v thilimit (nominally 50mv) drop across a sense resistor thus exceeding the programmed cr limit, the ISL6113, isl6114 enters its cr mode where it regulates the load current to the programmed level by modulating the gate of the related fet switch into t he linear region of operation to maintain 50mv across the sense resistor for the programmed t filter duration. however, should the load current cause a v rsense > v thfast , the outputs are immediately shut off with no t filter delay, as shown in fig ures 14 and 1 5. if the ISL6113, isl6114 latches off due to the t filter expiring, then the fets are turned-off more aggressively than if signaled from the linear region with approximately 80ma of gate current to ensure faster isolation from t he voltage bus. this is also true when turning off from a woc event. figure 10. isl6114 12vmain start-up r load = 10 ? , c load = 470f figure 11. isl6114 3vmain start-up r load = 2 ? , c load = 470f 12v out 12vgate c gd = open 12iout cfilter c gs = open 3v gate 3v out 3iout cfilter c gs = open figure 12. ISL6113 12vmain cr and shutdown figure 13. ISL6113 3vmain cr and shutdown 12v out 12vgate c filter 12iout cfilter 3vgate 3v out 3iout
ISL6113, isl6114 fn6457 rev 0.00 page 14 of 24 september 25, 2007 the vaux outputs have a differ ent circuit-breaker function. the vaux circuit breakers do not incorporate a fast-trip detector, instead they regulat e the current into a fault to avoid exceeding their operating current limit. the circuit breaker will trip due to an ov ercurrent on vaux when the programmable cr duration timer, t flt expires. this use of the t flt timer prevents the circuit breaker from tripping prematurely due to b rief current transie nts. see figures 16 and 17 for illustrations of the vaux protection performance into an over current (oc) an d more severe oc condition respectively. the i sl6113, isl6114 aux current control responds proportionally to the severity of the oc condition resulting in appropriately fas t vaux pull down and current regulation until t filter has expired. in the fault latch mode set by leaving l/r pin open, following a fault condition, the outputs can be turned on again via the on inputs (if the fault occurred on one of the main outputs), via the auxen inputs (if the fault occurred on the aux outputs), or by cycling both on and auxen (if faults occurred on both the main and aux outputs). when the circuit breaker trips, fault will be asserted. in the fault retry mode, set by grounding the l/r pin the ISL6113, isl6114 will initiate an automatic restart about eve ry 1.5s until successful. the ISL6113, isl6114 curren t regulation duration (t filter ) is set by external capacitors at the cfilter pins to gnd. once the cr mode is entered, t he external cap is charged with a 2.5a current source to 1.25v. once this threshold has been reached the ic then turns-off all fault the related fets and sets the fault output low. for a desired t filter , the value for c cfilter is given by equation 4: figure 14. ISL6113 12vmain woc shutdown figure 15. ISL6113 3vmain woc shutdown 12v out 12vgate 12iout cfilter cfilter 3 iout 3v out 3vgate figure 16. vaux oc regulation and shutdown figure 17. vaux woc regulation and shutdown cfilter vaux iaux cfilter vaux iaux c filter nominal t filter 500k ? -------------------------------------------- = (eq. 4)
ISL6113, isl6114 fn6457 rev 0.00 page 15 of 24 september 25, 2007 where 500k ? is (nominal v filter /nominal i filter ) and where t filter is the desired response time with the values for i filter and v filter being found in the ISL6113, isl6114s electrical specifications table on page 6. see table 3 for nominal t filter times for given c filter cap values. for the ISL6113, there is a minimum t filter consideration since the ISL6113 has its cr feat ure invoked as it turns-on the fets into the load. there is a maximum bulk capacitance specified for each power level supported that needs to be charged at the cr limit. this in-rush current time must be considered when pr ogramming the t filter . holding the cfilter pin low will increase the cr duration indefinitely. this feature may be useful in trouble shooting, o r evaluation. if this is invoked be cautious not to violate the soa of the pass fets. power-down cycle when signaled off, the gate pins are discharged/charged with a 25a for ISL6113 (5a for isl6114) current sink/source to ramp down the supplies in a controlled fashion. when a slot is turned off, internal switches a re connected to the outputs 12v out and 3v out providing a discharge path for load capacitance. this ensures tha t the outputs are pulled to gnd, thereby ensuring 0v on slot connectors during removal or insertion of add-in cards. thermal shutdown the internal vaux switches are protected against damage not only by current limiting, but b y a dual mode ov er-temperature protection scheme as well. each slot controller on the ISL6113, isl6114 is thermally isolated from the other. should an overcurrent condition raise the junction temperature of one slots controller an d pass switch > t over (nominally +140c), all of the outputs for that slot will be shut off and the slots fault output will be asserted. the other slots operating condition wi ll remain unaffected. however, should the ISL6113, isl6114s die temperature exceed +160c, all outputs for both slots will be shut off, whether or not a cu rrent limit condition exists. special i/o power good outputs (pwrgd ) the ISL6113, isl6114 have two open-drain, active-low pwrgd outputs that must be p ulled up to vstby. this output will be asserted when a slot has been enabled and the 12vmain, 3vmain and va ux outputs exceed their respective v uvth levels. pci-e reset outputs (perst ) a pci-express specif ic output, the ISL6113, isl6114 have two open-drain, active-low perst outputs that must be pulled up to vstby. upon enabli ng, the assertion high of perst is delayed a mini mum of 100ms (t pvperl ) from the power rails achieving minimum specified operating limits for stability of supplies and refclk. once high the card functions can safely start-up. perst is immediately pulled low when the power supply is disabled. force_on inputs (force_on ) these inputs are provided to fa cilitate system diagnostics or evaluation when usi ng the ISL6113, isl 6114. asserting a force_on input will turn on all th ree of the slots outputs, while over riding all three su pplies overcurrent, the main supplies uv protections, on-chip thermal prote ction for the vaux supplies and disable the pwrgd and fault outputs. asserting the force_on inputs will not disable the v uvlo(stby) . if not used, each pin should be connected to vstby. general purpose i/o (gpi, gpo) two pairs of pins on the isl61 13, isl6114 are available for buffered driving. both of th ese are compliant to 3.3v. if unused, connect each gpi pi n to gnd. the gpi pins are 5ms debounced for filt ering and the gpo are open drain capable of 90ma pull down c urrent for attention getting devices in accordance with the pci-express specifications. latch/retry operation toggle (l/r ) this input pin is tied to gnd f or a ~1.5s retry period after fault. if left open or tied high to vstby, the ISL6113, isl6114 will latch off upon a fault. board present input (prsnt ) the prsnt input is used to detect the presence of an add-in card in the slot. in systems where manual retention latch (mrl) is not implemented, this input detects when an add-in card is properly inserted into the slot via the last make, staggered length prsnt connection on the add-in card connector. this input must be pulled to ground through the add- in card ensuring all connecti ons have been m ade between the connector and the card in orde r to enable 3.3vaux turn-on. this pin function can be defaulted by tying to gnd. prsnt not being pulled low overrides and disables all force_on , on and auxen commands and for ~5ms after being pulled low. in systems where mrl is i mplemented this input is connected to the mrl sensor. the mrl sensor allows monitoring of the position of the mrl and the refore allows detection of unexpected openings of the mrl. these inputs are internally pulled up to the vstby rail. a ll i/o are valid at vstby <1v. table 3. nominal t filter duration c filter capacitance ( f) time (ms) open 0.01 0.01 5 0.022 11 0.047 24 0.1 50 note: nom. cr_dur = c filter cap (f) * 500k ? .
ISL6113, isl6114 fn6457 rev 0.00 page 16 of 24 september 25, 2007 pci-express application recommendations for each of the 3vmain and +12vmain supply, the cr level is set by an external sense resistor value depending on the maximum specified power fo r the various sizes of the pci-express connector and app lication implemented (x1, 10w or 25w; x4, x8, 25w; x16 , 25w or 75w; and x16 graphic-atx, 150w). the power rating is a combination of both main and the optional auxiliary supplies. this sense resistor i s a low sub-1 ? standard value current sense resistor (one for each slot) and the voltage across this resistor is compared to a 50m v reference. on the 12vmain, for a10w connector, a 75m ? sense resistor provides a no minal cr level of 0.66a, 32% above the 0.5a maximum specification; for a 25w connector, a 20m ? sense resistor provides a nominal cr level of 2.5a, 19% above the 2.1a maximum specific ation; for a 75w connector a 8m ? sense resistor provides a nominal cr level of 6.25a, 14% above the 5.5a maximum specif ication; for a x16 graphics- atx 150w card, a 7m ? sense resistor provides a nominal cr level of 7.1a, 14% above the 6.25a maximum specification. the 150w is provided by 2 slot s, each provid ing up to a maximum of 75w from the 12vmain as this specialized type of card does not consume 3vmain or aux supply power. the 3.3v supply uses a 15m ? sense resistor compared to a 50mv reference to provide a nominal cr of 3.3a or 11% above the 3a maximum specification load acro ss all sizes and power levels of the connector. table 4 provides recommen ded 12vmain sens e resistor values for particular power levels. providing a nominal cr protec tion level above the maximum specified limits of the card ens ures that the card is able to draw its maximum specified loads, and, in addition, have enough headroom before a re gulated current limiter is invoked to protect against tr ansients and other events. this headroom margin can be adjusted up or down by utilizing differing values of sense resistor. using the ISL6113eval1z, isl6114eval1z platform description and introduction the primary ISL6113, isl6114 evaluation platform is shown in figures 37 and 38 both photogr aphically and schematically. this evaluation board highlights a pcb layout that confines all necessary active and passi ve components in an area 12mmx55mm. this width is smaller than the specified pci-express socket to socket spacing allowing for intimate co-location of the load power c ontrol and the load itself. around the central highlighted l ayout are numerous labeled test points and configuration jumpers. where there are node names such as, ao(l/r ) the pin name in parentheses relates to the ISL6113, isl 6114. the ISL6113, isl6114 share an evaluation platform wi th the isl6112 as all three parts have a common pinout f or the common pin functions. the specific evaluation boar d as ordered and received will reflect the part number in the area below the intersil logo either by label or silk screened lettering. for those pins not common across the isl6112 an d ISL6113, isl6114 in the bottom left corner there is a m atrix detailing the differences. after correctly bia sing the evaluation platform as noted through the 6 bana na jacks, turni ng on vstby first then the other main supplies in any o rder. with the appropriate signaling to the auxen and o n inputs the user should see turn-on waveforms as shown previously. the addition of external current loading is necessary to demonstrate the oc and woc response performance. figures 18 and 19 demonstrate s ome of the pci-e specific and additional i/o functionality. figure 18 shows the prsnt pin being signaled low then the 12v out and 3v out outputs turning on automatically as the on input is already asserted. power good is signaled once the 12v out and 3v out meet their respective vuvvth levels. after the time period t pvperl the pci-e specific reset signal output, perst is asserted. figure 19 shows the gpi to gpo ~6ms functionality. figure 20 shows the retry period operation. approximately every 1.5s the ic attempts to restart into a faulty load until finally being able to turn-on fully into a normal load. this re try mode is invoked with r /l input tied low. ISL6113eval1z, isl6114eval1z errata gpo_a0 and gpo_bo labeli ng is reversed. correct labeling shown on evaluation board photograph in figure 37. caution: the ISL6113eval1z, isl6114eval1z gets very hot to the touch after operating it for a few min utes. hottest areas marked on evaluation board. table 4. nominal current regulation level 12vmain r sense (m ?? 12vmain cr (a) pci-e add in board power level supported (w) 75 0.7 10 20 2.5 25 86.2 75 77 150 note: cr level = vth ilimit /r sense .
ISL6113, isl6114 fn6457 rev 0.00 page 17 of 24 september 25, 2007 figure 18. prsnt , v out , powergood , perst figure 19. gpi to gpo functionality figure 20. retry mode operation t pvperl 3v out perst pgood 12vout prsnt gpo gpi 12vmain 12gate 3vmain 12iout
ISL6113, isl6114 fn6457 rev 0.00 page 18 of 24 september 25, 2007 typical performance curves figure 21. iccstby current vs temperature figure 22. icc current vs temperature figure 23. current limit threshold voltage vs temperature figure 24. fast trip threshold voltage vs temperature figure 25. aux current limit vs temperature figure 26. aux r ds(on) vs temperature 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0 -60 -40 -20 0 20 40 60 80 100 120 temperature (c) iccstby (ma) 0 0.2 0.4 0.6 0.8 1.0 -50 0 50 100 150 icc (ma) 3.3v icc 12v icc temperature (c) 47 48 49 50 51 52 53 -60 -40 -20 0 20 40 60 80 100 120 current limit vth (mv) temperature (c) 96 97 98 99 100 101 102 103 104 -60 -40 -20 0 20 40 60 80 100 120 woc threshold voltage (v) temperature (c) 800 850 900 950 1000 1050 1100 1150 1200 -60 -40 -20 0 20 40 60 80 100 120 aux current limit (ma) temperature (c) 200 220 240 260 280 300 320 340 360 380 400 -60 -40 -20 0 20 40 60 80 100 120 aux resistance ( ? ) iaux = 375ma temperature (c)
ISL6113, isl6114 fn6457 rev 0.00 page 19 of 24 september 25, 2007 figure 27. 12vmain rising por threshold voltage vs temperature figure 28. aux and 3vmain rising por threshold voltage vs temperature figure 29. 12vmain power good threshold voltage vs temperature figure 30. aux and 3vmain power good threshold voltage vs temperature figure 31. ISL6113 gate turn-on current (abs) vs temperature figure 32. isl6114 gate turn-on current (abs) vs temperature typical performance curves (continued) 9.05 9.10 9.15 9.20 9.25 9.30 -60 -40 -20 0 20 40 60 80 100 120 12vmain por rising (v) temperature (c) 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 -60 -40 -20 0 20 40 60 80 100 120 aux and 3vmain rising por (v) aux 3vmain temperature (c) 10.38 10.40 10.42 10.44 10.46 10.48 10.50 10.52 10.54 -60 -40 -20 0 20 40 60 80 100 120 12vmain uv vth (v) temperature (c) 2.70 2.71 2.72 2.73 2.74 2.75 2.76 2.77 2.78 2.79 2.80 -60 -40 -20 0 20 40 60 80 100 120 aux and 3vmain uv vth (v) aux 3vmain temperature (c) 22.0 22.5 23.0 23.5 24.0 24.5 25.0 25.5 -60 -40 -20 0 20 40 60 80 100 120 turn on curren t (a) 12v gate 3v gate temperature (c) 4.4 4.5 4.6 4.7 4.8 4.9 5.0 5.1 -60 -40 -20 0 20 40 60 80 100 120 turn on current (a) temperature (c) 12v gate 3v gate
ISL6113, isl6114 fn6457 rev 0.00 page 20 of 24 september 25, 2007 figure 33. gate fault off current (abs) vs temperature figure 34. filter charge current vs temperature figure 35. filter threshold volt age vs temperature figure 36. t pvperl vs temperature typical performance curves (continued) 0 20 40 60 80 100 120 -60 -40 -20 0 20 40 60 80 100 120 gate fault off current (ma) 3gate 12gate temperature (c) 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 -60 -40 -20 0 20 40 60 80 100 120 filter current (a) temperature (c) 1.20 1.22 1.24 1.26 1.28 1.30 -60 -40 -20 0 20 40 60 80 100 120 filter threshold (v) temperature (c) 130 135 140 145 150 155 160 -60 -40 -20 0 20 40 60 80 100 120 t pvperl (ms) temperature (c)
ISL6113, isl6114 fn6457 rev 0.00 page 21 of 24 september 25, 2007 figure 37. ISL6113eval1z, isl 6114eval1z board photograph gpo_a gpo_b caution hot area caution hot area caution hot area
fn6457 rev 0.00 page 22 of 24 september 25, 2007 ISL6113, isl6114 ISL6113 isl6114 figure 38. ISL6113eval1z, isl6114eval1z board schematic ISL6113, isl6114
fn6457 rev 0.00 page 23 of 24 september 25, 2007 ISL6113, isl6114 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2007. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. table 5. ISL6113eval1z, isl6114eval1z component listing component designator component function component description u1 ISL6113 or isl6114 pci-express dual slot hot plug controller q1, q4 voltage rail switches si4405dy or equivalent, p-channel mo sfet q2, q3 voltage rail switches si4820dy or equivalent, n-channel mo sfet r1, r3, r6, r8 current sense resistor 0.020 ? 1%, 2512 r9, r10, r17, r20 pull-up resistors on force_on and gpi inputs 100k ? , 0201 r11, r12, r13, 14, r15, r16, r18, 19, r21 i/o pull-up resistors 10k ? , 0201 r2, r4, r5, r7 fet gate series resistance 15 ? , 0201 c1, c7, c8, c13 ISL6113eval1z 3vmain fet gate capacitance 22nf 10 %, 16v, 0402 c1, c7, c8, c13 isl6114eval1z 3vmain fet gate capacitance open c3, c5, c6, c10, c11, c14 main and vstby decoupling capacitance 1f 10%, 6.3v, 0402 c2, c12 ISL6113 12vmain fet gate to drain capacitance 6.8nf 10%, 6.3v, 0201 c2, c12 isl6114 12vmain fet gate to drain capacitance open c4, c9 c filter capacitance (5ms) 0.01f 10%, 6.3v, 0201 r24, r25 aux load resistance 10 ? 20%, 3w c17, c18 aux load capacitance 100f 20%, 25v, radial electrolytic r22, r26, r28, 29 12vmain load resistance 20 ? 20%, 10w r23, r27 3vmain load resistance 2 ? 20%, 10w c15, c16, c19, c20 12vmain and 3vmain load capacitance 470f 20%, 16v, radial electrolytic
ISL6113, isl6114 fn6457 rev 0.00 page 24 of 24 september 25, 2007 package outline drawing l48.7x7 48 lead quad flat no-lead plastic package rev 4, 10/06 located within the zone indicate d. the pin #1 indentifier may b e unless otherwise specified, t olerance : decimal 0.05 tiebar shown (if present) i s a non-functional feature. the configuration of the pin #1 identifier is optional, but mus t be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing c onform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: 7.00 b a 7.00 (4x) 0.15 index area pin 1 top view pin #1 index area 44x 0.50 4x 5.5 48 37 4. 30 0 . 15 1 36 25 48x 0 . 40 0 . 1 4 m 0.10 c ab 13 24 bottom view 12 5 0 . 2 ref 0 . 00 min. 0 . 05 max. detail "x" c 0 . 90 0 . 1 base plane see detail "x" c c 0.08 seating plane c 0.10 side view typical recommended land pattern 6 6 ( 6 . 80 typ ) ( 4 . 30 ) ( 48x 0 . 60 ) ( 44x 0 . 5 ) ( 48x 0 . 23 ) 0.23 +0.07 / -0.05

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